The present invention relates to an improved digital phase locked loop, and more particularly relates to an improvement in function of a digital phase locked loop well suited for use in high speed circuits.
A wide variety of circuits have been developed to detect the displacement of a mobile object through demodulation of output signals from a detection encoder.
In one typical example of such detection circuits, is included a digital phase locked loop in which analog signals sin .theta. and cos .theta. corresponding to the displacement of a mobile object are issued by an encoder and digitalized for detection of the phase of the mobile object. More specifically, an encoder issues analog signals sin .theta. and cos.theta. corresponding to the angular displacement of a mobile object and these analog signals sin .theta. and cos .theta. are then digitalized by respective A/D converters. A function generating ROM is separately provided to issue signals sin .theta. and cos .theta. on the basis of its address data given by a counter of n-bits. These signals sin .phi. and cos .phi. are multiplied with the digitalized signals sin .theta. and cos .theta. by respective multipliers. The products of multiplication are then compared with each other by a comparator for calculation of a value sin (.theta.-.phi.). When the value sin (.theta.-.phi.) is positive, a signal U/D at "0" level is issued. Whereas a signal U/D at "1" level is issued when the value sin (.theta.-.phi.) is negative. The signal U/D is then passed to the above-described counter which also receives a series of prescribed clock pulses. On receipt of the signal U/D at "0" level, the counter operates in an up-count mode. Whereas the counter operates in a down-count mode on receipt of the signal U/D at "1" level. Output signals from the counter are properly latched at rises of the signal U/D.
In the case of such a detection circuit, the digital phase locked loop operates so that the value sin (.theta.-.phi.) should always be equal to 0, i.e. .theta. should always be equal to .phi.. In other words, the output signal from the counter corresponds to the angular displacement .theta. of the mobile object. Even when the signal vacillates between "0" and "1" levels as the value sin (.theta.-.phi.) approaches 0, presence of a latch removes fluctuation in output. Such a detection circuit is proposed in Japanese Patent Application 61-54288.
It is assumed that a counter of 8-bits and clock pulses of 2 MHz are used in the above-described detection circuit, the maximum frequency that the loop can process is equal to 2 MHz/256=7.8 KHz. In the case of high speed mobile objects, the frequencies of their input signals often exceeds 7.8 KHz and the loop is unable to process such input signals. So, high speed signal processing by digital phase locked loops has been strongly demanded in the market. In connection with this, limitation in the access speed of the function generating ROM and in the processing speed of the comparator forms a neck to use clock pulses of higher frequencies. Further, a time must be reserved for operations of the A/D converters. For these reasons, higher speed signal processing of digital phase locked loops cannot be expected despite the strong demand in the market.